1. Field of the Invention
The present invention relates to a memory reading circuit, and more specifically to a memory reading circuit for an SRAM (static random access memory) and an SRAM having a memory reading circuit.
2. Description of Related Art
Recently, development of a micro-miniaturization of semiconductor devices is remarkable, and in the SRAM formed of semiconductor devices, a low power consumption and a high speed operation are demanded. In a read/write operation proportion of the SRAM, the reading operation generally occupies 70% to 80% of the whole operation. Therefore, in order to reduce the power consumption in the SRAM, it is effective to reduce the power consumption in the reading operation. On the other hand, the factor determining the operation speed of the SRAM is an access time in the reading operation. Therefore, in order to speed up the operation of the SRAM, it is necessary to reduce the access time in the reading operation.
One technology for speeding up the reading operation of the SRAM is disclosed in Japanese Patent Application Pre-examination Publication No JP-A-09-231767, (an English abstract of JP-A-09-231767 is available and the content of the English abstract of JP-A-09-231767 is incorporated by reference in its entirety into this application). This prior art describes a method for controlling the generating timing of a signal for enabling a sense amplifier by the number of gates. However, this prior art does not touch the reduction of the power consumption.
Referring to FIG. 1, there is shown a block diagram illustrating the construction of a conventional SRAM for making it easier to understand the present invention which will be described later.
The SRAM shown in FIG. 1 is a synchronous SRAM, and includes a memory cell array 10 composed of a number of memory cells 12 arranged in the form of an X-Y matrix. Each of the memory cells 12 is connected, in units of a Y direction column, to a bit line charge circuit 18 and a bit line selection circuit 20 through a pair of complementary bit lines 14 and 16. In addition, the memory cells on the same line in an X direction are connected through a corresponding word line 22 to a sense amplifier activation timing generator 25, which is connected to an X address decoder 38. The bit line selection circuit 20 is connected to a sense amplifier 24 and a write circuit 26, and the sense amplifier 24 is connected to an output circuit 28. The output circuit 28 and the write circuit 26 are connected to a data input/output line 30.
The bit line selection circuit 20 is also connected to a Y address decoder 32. A clock signal control circuit 34 is connected to supply a precharge signal PS to the sense amplifier 24, the sense amplifier activation timing generator 25, and the bit line charge circuits 18, and the precharge signal PS is also supplied through an inverter 36 to the X address decoder 38. The sense amplifier activation timing generator 25 is connected to supply a sense amplifier enabling signal SAE to the sense amplifier 24, and the sense amplifier enabling signal SAE is also supplied through an inverter 40 to the X address decoder 38. A write control circuit 42 is connected to supply a write signal WS to the sense amplifier activation timing generator 25 and the write circuit 26.
Referring to FIG. 2, there is shown a circuit diagram illustrating the construction of the sense amplifier activation timing generator 25. The sense amplifier activation timing generator 25 is constituted of MOS transistors, NAND gates, etc. This sense amplifier activation timing generator 25 generates the signal SAE for enabling the sense amplifier and a signal SAEB for deactivating the word line.
Now, a reading operation of the SRAM shown in FIG. 1 will be described with reference to a timing chart of FIG. 3 illustrating the reading operation. In FIG. 3, "A" indicates an external clock signal OCLK, and "B" shows the precharge signal PS. "C" indicates the signal SAEB for deactivating the word line (in the reading time), and "D" shows a period in which the word line is active. "E" indicates the signal SAE for enabling the sense amplifier. "F" shows the potential of the complementary bit line pair 14 and 16, and "G" indicates the potential of a complementary bit line pair 15 and 17 outputted from the bit line selection circuit 20.
The clock signal control circuit 34 generates, on the basis of the external clock OCLK, the precharge signal PS having a phase delayed from the external clock OCLK. On the other hand, an X address and a Y address are decoded by the X address decoder 38 and the Y address decoder 32. The sense amplifier activation timing generator 25 generates the signal SAE for enabling the sense amplifier. This signal SAE is inverted by the inverter 40, and the inverted signal SAEB is supplied to the X address decoder 38 for deactivating the word line 22 which is an X row selection line for activating the memory cells on the same line. The precharge signal PS is inverted by the inverter 36, and the inverted signal PSB (not shown in FIG. 3) is supplied to the X address decoder 38.
With a falling of the precharge signal PS, the bit line charge circuit 18 precharges the complementary bit line pair 14 and 16, and thereafter, with a falling of the signal PSB, the word line 22 is activated, so that the memory cell is selected. The selected memory cell begins to discharge, so that a potential difference is generated between the pair of complementary bit lines 14 and 16. On the other hand, with a rising of the precharge signal PS, the sense amplifier activation timing generator 25 starts the discharge operation, so that the signal SAE becomes a high level after a delay time determined by the dimension (gate width) of the transistors included in the sense amplifier activation timing generator 25 shown in FIG. 2 In response to the high level of the signal SAE, the sense amplifier 24 operates. With a falling of the signal SAEB, the word line 22 is brought to a low level, so that the selection of the memory cell to be read is completed.
In the timing chart "D" in FIG. 3, the timing for deactivating the word line is indicated by a time t.sub.1 counted from the rising of the external clock signal OCLK, and in the timing chart "E" in FIG. 3, the timing for bringing the signal SAE to the high level is indicated by a time t.sub.2 counted from the rising of the external clock signal OCLK. These times t.sub.1 and t.sub.2 are determined by the delay time which is determined by the gate width of the transistors included in the sense amplifier activation timing generator 25, as mentioned above.
The timing where the sense amplifier 24 operates, is determined to be later than a time that a potential swing amplitude .DELTA.V1 on the complementary bit line pair 14 and 16 connected to the selected memory cell to be read (the potential difference between the pair of complementary bit lines 14 and 16), namely, the potential swing amplitude .DELTA.V2 on the complementary bit line pair 15 and 17 (the potential difference between the pair of complementary bit lines 15 and 17) outputted from the bit line selection circuit 20 in the circuit shown in FIG. 1, becomes higher than a minimum operating voltage of the sense amplifier 24.
In the power consumption of the prior art SRAM shown in FIG. 1, the power consumed by the memory cell array is dominant. Considering the SRAM of 512 W.times.16 bit as an example, about 50% of the whole power consumption in the reading operation is the power consumed by the memory cell array, and the remaining 50% is consumed by and the other circuits including the decoder, the sense amplifier and the output circuit. Specifically, the power consumption of the memory cell array is mainly attributable to the charging current and the discharging current of the bit line pairs. Generally, the charging current and the discharging current is determined by the following equation: EQU I=f.times.c.times..DELTA.V
where "f" is an operating frequency, "c" is a bit line load capacitance, and ".DELTA.V" is a potential swing amplitude.
Here, assuming that the swing amplitude of the potential in the bit line pair is .DELTA.V1 and the number of the memory cells arranged in the X direction (word line direction) is n, when the word line is activated, all the memory cells on the same line are driven, so that the potential difference is generated in the "n" bit line pairs. Therefore, a total .DELTA.V is expressed as follows: EQU .DELTA.V=n.times..DELTA.V1
Accordingly, the current I.sub.cell of the memory cell array is expressed as follows: EQU I.sub.cell =f.times.c.times.n.times..DELTA.V1
Therefore, assuming that the frequency "f" and the load capacitance "c" are constant, if the potential swing amplitude .DELTA.V1 in the bit line pair becomes "m" times, the current of the memory cell also becomes "m" times. Accordingly, the power consumption in the memory cell array depends upon the potential swing amplitude .DELTA.V1 in the bit line pair.
On the other hand, the reading speed of the SRAM depends upon the output timing of the signal SAE. In the construction of the prior art SRAM shown in FIG. 1, the timing for operating the sense amplifier is determined by the construction of the sense amplifier activation timing generator and the gate width of the transistors included in the sense amplifier activation timing generator.
In the above mentioned prior art SRAM, the following problems have been encountered.
(1) In the SRAM (particularly, the SRAM disclosed in JP-A-09-231767), the speed-up of the reading operation and the reduction of the power consumption cannot be simultaneously realized. PA1 (2) Since the gate width of the transistors included in the sense amplifier activation timing generator is determined by a diffusion process in a manufacturing process, an optimum design is difficult in the SRAM designing. PA1 (3) Similarly, since the gate width of the transistors included in the sense amplifier activation timing generator is determined by a diffusion process in a manufacturing process, a feedback obtained from the evaluation on an actual chip needs a considerable time in the SRAM designing, and therefore, a long TAT (development time) is required. PA1 (1) Assuming that .DELTA.Vmin is a minimum value of the potential swing amplitude in the bit line pair, required to cause the sense amplifier to operate, a delayed inverted signal DPSB of the precharge signal PS is generated by a delay circuit to the effect that .DELTA.V2=.DELTA.Vmin is satisfied in the falling of the word line in the SRAM reading operation; and PA1 (2) The delay circuit is designed to make the timing of the falling of the word line and the timing of the activation of the sense amplifier (namely, the rising of the signal SAE) consistent with each other in the reading operation, namely, t.sub.1 =t.sub.2.